Elevated and non-uniform temperatures can negatively impact the reliability of flash memory devices, such as multi-level cell (MLC) NAND and solid state drive (SSD) products. Such reliability impacts become more pervasive as the sizes of flash memory devices are scaled down. In one example, a gradient temperature difference may be present between a top die and a bottom die of a memory stack. In another example, a temperature may be disproportionately higher within a bay of SSDs where heavy write activity is executed. Such temperature gradients can accelerate charge loss and reduce data retention capabilities, leading to increased error rates in the flash memory devices.
Conventional solutions provide error-correcting code (ECC) correction processing that accounts for worst case error scenarios. The same ECC profile is applied to all devices irrespective of position and actual thermal characteristics. The approach can compromise overall ECC efforts. For example, setting the ECC point based on the worst-case temperature profile can result in flash memory consuming more space for ECC blocks than is necessary. Adding more ECC capability can introduce higher latencies and memory requirements, while contributing to less endurance and retention.